Team VLSI
Team VLSI
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Derivation for Setup and Hold equations | between +ve and -ve flip flops | Half cycle path | Part-2
Setup and Hold Time equation between positive and negative edge triggered flip flops have been derived. Such a path is called a Half cycle path. Setup and hold time equations have been derived step by step with easy explanation. The flow of this session is as follow:
0:00 Introduction
1:20 Derivation for setup equation from a negative edge triggered FF to a Positive edge-triggered FF
9:00 Summary of setup time calculation
11:32 Derivation for Hold Equation from a negative edge triggered FF to a Positive edge-triggered FF
18:20 Summary of hold time calculation
20:25 Thanks
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Related videos:
Setup and Hold equation be...
Просмотров: 7 515

Видео

Derivation for Setup and Hold time equations | in Flip Flop | With Numerical example | Part -135:16Derivation for Setup and Hold time equations | in Flip Flop | With Numerical example | Part -1
Derivation for Setup and Hold time equations | in Flip Flop | With Numerical example | Part -1
Просмотров 9 тыс.2 года назад
How to derive the setup and hold time equation for two flip flops has been explained in this session. The timing equation has been derived in a very easy way that will be easy to understand for everyone. Setup and Hold equation has been derived step by step with complete celebration. To make the theory more understandable, numerical examples for setup and hold time has also been given and solve...
Common Path Pessimism Removal in VLSI | CPPR in VLSI | CRPR in VLSI22:27Common Path Pessimism Removal in VLSI | CPPR in VLSI | CRPR in VLSI
Common Path Pessimism Removal in VLSI | CPPR in VLSI | CRPR in VLSI
Просмотров 15 тыс.2 года назад
Common Path Pessimism Removal (CPPR) is a way to make Static Timing Analysis more accurate and it removes the extra pessimism added in the common clock path. In this video we have discussed Common Clock Point, Common Clock Point, Common Path Pessimism and the way of calculating Common Path Pessimism in OCV and SOCV with example. The flow of discussion is as flow. || RELATED Topics || STA Playli...
Signoff order in Physical Design | Various signoff in VLSI | Signoff Checks7:41Signoff order in Physical Design | Various signoff in VLSI | Signoff Checks
Signoff order in Physical Design | Various signoff in VLSI | Signoff Checks
Просмотров 6 тыс.2 года назад
Signoff is the final stage in ASIC design where we close the design against all the design rule checks in order the make sure our design will work properly after fabrication and it is flawless. The order of design closer is also important we have to follow a certain order in design closer. In this session basically, the various signoff checks and their order have been discussed. The flow and ti...
Placement Steps in Physical Design | pre placement and placement steps in VLSI16:12Placement Steps in Physical Design | pre placement and placement steps in VLSI
Placement Steps in Physical Design | pre placement and placement steps in VLSI
Просмотров 13 тыс.2 года назад
Placement is a major step in Physical design. PnR tool does various steps to complete the placement step. The major steps of placement have been explained in this session with proper examples and illustrations. The pre-placement steps like pin placement, macro placement, placement blockage, routing blockage, power plan, end cap cell placement, well tap cell placement etc. have also been explain...
Virtual Box + CentOS Installation on window 10 | Download CentOS | Install Linux20:49Virtual Box + CentOS Installation on window 10 | Download CentOS | Install Linux
Virtual Box + CentOS Installation on window 10 | Download CentOS | Install Linux
Просмотров 2 тыс.2 года назад
In this video, installation of the virtual box has been demonstrated first later we have installed CentOS 7 on the virtual box. How to download the virtual box and CentOS .iso file all have been shown in this video. If you feel this video is useful, please like the video and subscribe to this channel to get more such videos in future. Your queries/suggestions are most welcome in the comment sec...
Integrated Clock Gating Cell | ICG Cell in VLSI | Clock Gating Cell | Low Power Techniques in VLSI9:35Integrated Clock Gating Cell | ICG Cell in VLSI | Clock Gating Cell | Low Power Techniques in VLSI
Integrated Clock Gating Cell | ICG Cell in VLSI | Clock Gating Cell | Low Power Techniques in VLSI
Просмотров 15 тыс.2 года назад
Integrated clock gating or ICG Cell or Clock gater cell is used to control the clock signal to a sequential element or group of elements. The clock gating technique is one of the most popular techniques used in low power design techniques. In this video, the need for ICG Cell, the structure of ICG Cell, and the Function of ICG cells has been described in detail. The flow of the video is given b...
Setup and Hold time inside Latch16:33Setup and Hold time inside Latch
Setup and Hold time inside Latch
Просмотров 11 тыс.3 года назад
The reason for Setup and Hold timing requirement inside latch has been explained in a simplified manner. To explain the topic a brief introduction about the design of latch in terms of the multiplexer, transmission gate and transistor has also been discussed. The working principle of the latch is the most important part to understand the topic. Latching edge and setup and hold timing equations ...
Latch and Flip Flops in ASIC Design21:54Latch and Flip Flops in ASIC Design
Latch and Flip Flops in ASIC Design
Просмотров 8 тыс.3 года назад
The logic circuit, transistor-level circuit and functions of the latch and flip flop have been explained in this video tutorial. Operation of the latch and the flip flop has been demonstrated with the example of the waveform. And finally summarized the main points and differences in latch and flip flop. The flow of this tutorial is as follow. 0:00 Introduction 1:30 Logic Design 2:28 Latch and F...
Setup and Hold Equations S-02 | In Positive and Negative Edge Triggered Flip Flop | Half Cycle Path21:30Setup and Hold Equations S-02 | In Positive and Negative Edge Triggered Flip Flop | Half Cycle Path
Setup and Hold Equations S-02 | In Positive and Negative Edge Triggered Flip Flop | Half Cycle Path
Просмотров 8 тыс.3 года назад
When the data is launched by a positive edge-triggered FF and Captured by Negative Edge Triggered FF or vice-versa, The equations get changed from the normal setup and hold equation. In this video, these equations have been explained in an easy way. The timeline of this video is as follow. 0:00 Introduction 1:10 Agenda of the session 1:40 Derivation of setup equation 8:40 Setup Slack 11:20 Half...
Setup and Hold Timing Equations - S-01| Easy Explanation with Examples | Same types of FF40:08Setup and Hold Timing Equations - S-01| Easy Explanation with Examples | Same types of FF
Setup and Hold Timing Equations - S-01| Easy Explanation with Examples | Same types of FF
Просмотров 16 тыс.3 года назад
Timing is everything for an ASIC design and Setup and Hold timing analysis is an important aspect in timing signoff of ASIC. The Setup and Hold Timing equations have been derived in this tutorial in a very easy way. Timing analysis has been explained with some relevant example and way of fixing the setup and hold has also been explained. Timeline of Video: 0:00 Introduction 0:45 Possible scenar...
Clock Uncertainty in VLSI | Why clock uncertainty | Factors in Clock Uncertainty16:42Clock Uncertainty in VLSI | Why clock uncertainty | Factors in Clock Uncertainty
Clock Uncertainty in VLSI | Why clock uncertainty | Factors in Clock Uncertainty
Просмотров 19 тыс.3 года назад
Clock uncertainty has been discussed in this session. The discussion flow of the tutorial is as follow: 0:00 Introduction 1:20 Jitter of Clock 2:20 Skew of clock 4:10 Other expected variations in clock 4:35 Clock Uncertainty 8:20 Factors in clock uncertainty 9:05 preCTS setup uncertainty 9:28 preCTS hold uncertainty 10:35 postCTS setup uncertainty 11:32 postCTS hold uncertainty 11:40 set_clock_...
Clock Skew in VLSI | Positive Skew | Negative Skew | Global Skew | Local Skew9:35Clock Skew in VLSI | Positive Skew | Negative Skew | Global Skew | Local Skew
Clock Skew in VLSI | Positive Skew | Negative Skew | Global Skew | Local Skew
Просмотров 13 тыс.3 года назад
Clock Skew has been explained in this session in details. What is clock skew in VLSI, Why clock skew occurs, What is positive skew, What is negative skew, What is global skew and What is local skew, all these are explained in this video tutorial. The flow of this session is as follow. 0:00 Introduction 0:40 Clock Skew 4:29 Positive skew 5:19 Negative skew 6:12 Question 6:45 Local Skew 7:05 Glob...
Data and Clock Path | Launch and Capture Flops | Cell delay | Net Delay12:36Data and Clock Path | Launch and Capture Flops | Cell delay | Net Delay
Data and Clock Path | Launch and Capture Flops | Cell delay | Net Delay
Просмотров 8 тыс.3 года назад
Data and clock path has been explained in this video along with Launch clock path and Capture Clock path. Start and Endpoints, launch and capture flops, Clock to Q delay, Combinational Delay, Cell delay and Net Delay have also been explained in this video. The flow of this video is like this: 0:00 Introduction 0:50 Data and Clock paths 4:10 Launch and Capture clock paths 5:47 Launch and Capture...
Clock Latency in VLSI | Source Latency | Network Latency | Insertion Delay9:35Clock Latency in VLSI | Source Latency | Network Latency | Insertion Delay
Clock Latency in VLSI | Source Latency | Network Latency | Insertion Delay
Просмотров 11 тыс.3 года назад
Clock latency has been explained in this video tutorial along with clock source latency and clock network latency and Insertion delay. We have also discussed the command to specify the clock latency set_clock_latency in SDC file. The flow of the video is like follow. 0:00 Introduction 0:47 Clock Latency 4:26 Source and Network Latency 5:57 Insertion Delay 6:28 set_clock_latency command If you f...
RTL to GDSII flow | Introduction of RTL to GDS Flow | Various EDA tools used in RTL to GDS flow17:37RTL to GDSII flow | Introduction of RTL to GDS Flow | Various EDA tools used in RTL to GDS flow
RTL to GDSII flow | Introduction of RTL to GDS Flow | Various EDA tools used in RTL to GDS flow
Просмотров 16 тыс.3 года назад
RTL to GDSII flow | Introduction of RTL to GDS Flow | Various EDA tools used in RTL to GDS flow
Basics of Clock Signal | Characteristics of Clock | Property of Digital Clock22:19Basics of Clock Signal | Characteristics of Clock | Property of Digital Clock
Basics of Clock Signal | Characteristics of Clock | Property of Digital Clock
Просмотров 10 тыс.3 года назад
Basics of Clock Signal | Characteristics of Clock | Property of Digital Clock
Reason for Setup and hold time in flip flop | Setup and hold time | clock to q delay | FF using Mux33:26Reason for Setup and hold time in flip flop | Setup and hold time | clock to q delay | FF using Mux
Reason for Setup and hold time in flip flop | Setup and hold time | clock to q delay | FF using Mux
Просмотров 29 тыс.4 года назад
Reason for Setup and hold time in flip flop | Setup and hold time | clock to q delay | FF using Mux
False Path in VLSI | Examples of false path | Write false path constraints | Timing exceptions10:35False Path in VLSI | Examples of false path | Write false path constraints | Timing exceptions
False Path in VLSI | Examples of false path | Write false path constraints | Timing exceptions
Просмотров 14 тыс.4 года назад
False Path in VLSI | Examples of false path | Write false path constraints | Timing exceptions
Multi cycle path in VLSI | Multi cycle path Constraint | Multi cycle path example17:38Multi cycle path in VLSI | Multi cycle path Constraint | Multi cycle path example
Multi cycle path in VLSI | Multi cycle path Constraint | Multi cycle path example
Просмотров 18 тыс.4 года назад
Multi cycle path in VLSI | Multi cycle path Constraint | Multi cycle path example
Temperature Inversion in VLSI | Cell Delay variation with Temperature19:56Temperature Inversion in VLSI | Cell Delay variation with Temperature
Temperature Inversion in VLSI | Cell Delay variation with Temperature
Просмотров 24 тыс.4 года назад
Temperature Inversion in VLSI | Cell Delay variation with Temperature
Equations writing in LaTex | Equation copying from another place to LaTex | MathPix snaping tool4:17Equations writing in LaTex | Equation copying from another place to LaTex | MathPix snaping tool
Equations writing in LaTex | Equation copying from another place to LaTex | MathPix snaping tool
Просмотров 1,5 тыс.4 года назад
Equations writing in LaTex | Equation copying from another place to LaTex | MathPix snaping tool
URL Citation in LaTex | How to cite URL /web link in LaTex2:49URL Citation in LaTex | How to cite URL /web link in LaTex
URL Citation in LaTex | How to cite URL /web link in LaTex
Просмотров 41 тыс.4 года назад
URL Citation in LaTex | How to cite URL /web link in LaTex
Ecosystem of Semiconductor Industry -II | Overview of VLSI Industries | ASIC Industry in a glance25:37Ecosystem of Semiconductor Industry -II | Overview of VLSI Industries | ASIC Industry in a glance
Ecosystem of Semiconductor Industry -II | Overview of VLSI Industries | ASIC Industry in a glance
Просмотров 2,5 тыс.4 года назад
Ecosystem of Semiconductor Industry -II | Overview of VLSI Industries | ASIC Industry in a glance
Ecosystem of Semiconductor Industry -I | Overview of VLSI Industries | ASIC Industry in a glance27:45Ecosystem of Semiconductor Industry -I | Overview of VLSI Industries | ASIC Industry in a glance
Ecosystem of Semiconductor Industry -I | Overview of VLSI Industries | ASIC Industry in a glance
Просмотров 5 тыс.4 года назад
Ecosystem of Semiconductor Industry -I | Overview of VLSI Industries | ASIC Industry in a glance
OCV, AOCV and POCV : a comparative study | difference among OCV, AOCV and POCV | Process Variations34:00OCV, AOCV and POCV : a comparative study | difference among OCV, AOCV and POCV | Process Variations
OCV, AOCV and POCV : a comparative study | difference among OCV, AOCV and POCV | Process Variations
Просмотров 33 тыс.4 года назад
OCV, AOCV and POCV : a comparative study | difference among OCV, AOCV and POCV | Process Variations
GDS & OASIS file | Graphical Design System | Need of OASIS over GDSII file | gdsII file | OASIS file12:52GDS & OASIS file | Graphical Design System | Need of OASIS over GDSII file | gdsII file | OASIS file
GDS & OASIS file | Graphical Design System | Need of OASIS over GDSII file | gdsII file | OASIS file
Просмотров 9 тыс.4 года назад
GDS & OASIS file | Graphical Design System | Need of OASIS over GDSII file | gdsII file | OASIS file
SPEF file in VLSI | Standard Parasitic Exchange Format file | .spef file in Physical Design27:16SPEF file in VLSI | Standard Parasitic Exchange Format file | .spef file in Physical Design
SPEF file in VLSI | Standard Parasitic Exchange Format file | .spef file in Physical Design
Просмотров 12 тыс.4 года назад
SPEF file in VLSI | Standard Parasitic Exchange Format file | .spef file in Physical Design
Filler Cell | Filler Cell in ASIC Design Flow | Layout of Filler Cell26:28Filler Cell | Filler Cell in ASIC Design Flow | Layout of Filler Cell
Filler Cell | Filler Cell in ASIC Design Flow | Layout of Filler Cell
Просмотров 13 тыс.4 года назад
Filler Cell | Filler Cell in ASIC Design Flow | Layout of Filler Cell
Tie Cell in ASIC Design | Use of Tie cell | Schematic and Layout of Tie cells | How Tie cells work17:04Tie Cell in ASIC Design | Use of Tie cell | Schematic and Layout of Tie cells | How Tie cells work
Tie Cell in ASIC Design | Use of Tie cell | Schematic and Layout of Tie cells | How Tie cells work
Просмотров 9 тыс.4 года назад
Tie Cell in ASIC Design | Use of Tie cell | Schematic and Layout of Tie cells | How Tie cells work

Комментарии

  • @shreyanshsoni6148
    @shreyanshsoni6148 15 дней назад

    if delay is decreasing as the temperature is increasing and the circuit is becoming faster then it will generate more heat, so temperature will increase further which will form a positive loop and can damage the circuit.... am i right

  • @komarashiva2091
    @komarashiva2091 17 дней назад

    Sir in pre-cts u mentioned latency is negligible then how u calculate the skew(capture latency - launch latency)

  • @ravikumara7496
    @ravikumara7496 18 дней назад

    Password

  • @sridharchandrasekar7787
    @sridharchandrasekar7787 19 дней назад

    Nice lecture bro...i have one doubt..how to design memory by using pdk

  • @aalabalu674
    @aalabalu674 22 дня назад

    Great explanation sir🎉❤

  • @Kim-jx6vq
    @Kim-jx6vq 23 дня назад

    How this amazing lecture is free. Many thanks to you from Korea

    • @TeamVLSI
      @TeamVLSI 23 дня назад

      Thanks a lot for your appreciation; Best wishes from India :)

  • @Jamboreeni
    @Jamboreeni Месяц назад

    Can you please explain how reducing wire length will help in EM?

    • @Jamboreeni
      @Jamboreeni Месяц назад

      Sorry got it, Blech length

  • @saisrikarthirukovela9219
    @saisrikarthirukovela9219 Месяц назад

    Whatsapp invite linked seems to be modified. Can you please share the updated one.

    • @TeamVLSI
      @TeamVLSI 27 дней назад

      Thanks @saisrikarthirukovela9219 Please join using below link, and you may share to others as well. chat.whatsapp.com/HzCxJjtXgLP9j13R7m5HHq

  • @sairamsmart2779
    @sairamsmart2779 Месяц назад

    Is there any active whatsapp or Telegram group link?

    • @TeamVLSI
      @TeamVLSI 27 дней назад

      Yes, please join. chat.whatsapp.com/HzCxJjtXgLP9j13R7m5HHq

  • @sungmeenmyung6084
    @sungmeenmyung6084 Месяц назад

    Thank you for the video.

    • @TeamVLSI
      @TeamVLSI 27 дней назад

      Thank you :)

  • @satyasudha8925
    @satyasudha8925 Месяц назад

    nice way of explanation.

  • @radhaa6564
    @radhaa6564 Месяц назад

    Please make video on data to data checks,its very helpfull

  • @officialananthanm6545
    @officialananthanm6545 Месяц назад

    For me corner cells are not found.. I have double checked the .io file..syntax is okay..

  • @deepakbabu720
    @deepakbabu720 2 месяца назад

    can you make a video on clock exceptions in cts

  • @ThuyPham-sk9ju
    @ThuyPham-sk9ju 2 месяца назад

    so what is diffenent between tlu and tlu+?

  • @ArunChikkaraju
    @ArunChikkaraju 2 месяца назад

    I have one doubt You have said that the std cell height should be fixed and width can be varied but in 27:42 we have cells with various heights can anyone explain about this scenario?

  • @IC_design_Bellamkonda
    @IC_design_Bellamkonda 2 месяца назад

    Is there any standard to differentiate the lower and higher technology nodes. Like 65n you mentioned.

  • @IC_design_Bellamkonda
    @IC_design_Bellamkonda 2 месяца назад

    Excellent flow to understand the concept. There are many resources with concepts in statements but you have given nicely explained from equations to concepts towards statements. Great work bro. ❤

  • @abdelazeem201
    @abdelazeem201 2 месяца назад

    Using FILL1 cells where you can use FILL16/8 is generally not recommended due to several potential issues that can arise: Metal Slotting: When you replace larger filler cells (FILL16/8) with multiple smaller filler cells (FILL1), the design may end up with narrow metal gaps. These gaps can cause slotting in the metal layers, which can degrade the integrity and performance of the interconnects. Metal Dishing: Metal dishing occurs during the Chemical Mechanical Polishing (CMP) process. It happens when the metal surface becomes uneven due to over-polishing. Using many small filler cells instead of fewer larger ones can exacerbate this issue, leading to uneven metal layers. Dielectric Erosion: Similar to metal dishing, dielectric erosion is the excessive removal of dielectric material during the CMP process. An increased number of small cells can create more areas where the dielectric material is unevenly polished away, leading to erosion. In summary, while it might be tempting to use smaller filler cells due to availability or other reasons, it introduces risks related to the integrity and performance of the metal interconnects and the dielectric material in the design. Therefore, it's better to use the appropriately sized filler cells (FILL16/8) as intended to avoid these issues.

  • @Akk-ei9uw
    @Akk-ei9uw 3 месяца назад

    Do we do IR analysis in schematic or layout

  • @Akk-ei9uw
    @Akk-ei9uw 3 месяца назад

    can you suggest a tool to find out crosstalk in the layout drawn? is there any opensource tools? What will be its input?

  • @andrewlukkuz369
    @andrewlukkuz369 3 месяца назад

    The soundtrack goes hard.

  • @rohanyadala9096
    @rohanyadala9096 4 месяца назад

    Excellent

  • @rohanyadala9096
    @rohanyadala9096 4 месяца назад

    Excellent

  • @user-bj7pr7gz5x
    @user-bj7pr7gz5x 4 месяца назад

    i am from INDIA... classes are very useful / Thank you SIR

  • @saraghomi3970
    @saraghomi3970 4 месяца назад

    Could you please provide the installation process of TCAD synopsys sentaurus in Centos 7?

  • @sharathseshadri3634
    @sharathseshadri3634 5 месяцев назад

    Keep length short ???

  • @joshnareddy7480
    @joshnareddy7480 5 месяцев назад

    Can you please do video on clock gating and asynchronous checks in vlsi

  • @prashantmathur52
    @prashantmathur52 5 месяцев назад

    Really good video!!

  • @taraldc
    @taraldc 5 месяцев назад

    Very nicely explain SDC

  • @rohanyadala9096
    @rohanyadala9096 5 месяцев назад

    Very nice...

  • @HarNilBandhiya
    @HarNilBandhiya 5 месяцев назад

    Decap me gate tunneling leakage hoga

  • @HarNilBandhiya
    @HarNilBandhiya 5 месяцев назад

    5:11 start explaining layout of end cap

  • @HarNilBandhiya
    @HarNilBandhiya 5 месяцев назад

    Clear explanation sir

  • @bharathhm2215
    @bharathhm2215 5 месяцев назад

    Hi.. this video is one of the best explanations on the Setup & Hold topic. Thanks! So I have a doubt - For any flip flop will the Clk to Q delay be the same as the Hold time because both have a Tg delay + Inverter delay?

  • @MrBabajikijai
    @MrBabajikijai 5 месяцев назад

    good video

  • @pvignesh6253
    @pvignesh6253 6 месяцев назад

    Thanks for the session 🙏

  • @janicesweedal4877
    @janicesweedal4877 6 месяцев назад

    Temp is low for hold in worst case

  • @harikrishnanperumalsamy6788
    @harikrishnanperumalsamy6788 6 месяцев назад

    Could you please share the sdevice coding for ID vs Vg.

  • @kaverihatti686
    @kaverihatti686 6 месяцев назад

    HOW TO GET THE SYNAPSIS LIBRARY FILES

  • @kaverihatti686
    @kaverihatti686 6 месяцев назад

    what are the files to download to work? with hspice simulator in cadence

  • @thatdrownedbiscuit
    @thatdrownedbiscuit 6 месяцев назад

    Sir The content is top-notch But maybe can we eliminate the background noise?

  • @techpiku1
    @techpiku1 7 месяцев назад

    Can I get finfet

  • @dhadikaryt7308
    @dhadikaryt7308 7 месяцев назад

    sir i have two doubt, can u pls answer me Miss loading one timing library explicitly and give the check_library for the errors in the report. Miss loading one physical library explicitly and give the check_library for the errors in the report. how to check these two ?

  • @anujparekh752
    @anujparekh752 7 месяцев назад

    What is difference between .lef and .tf? how they exactly have some difference?

  • @lavanyaekkandolla8512
    @lavanyaekkandolla8512 8 месяцев назад

    Hi, how to read the multiple files ( hierarchical design) in the dc shell? Is there any option to read the filelist?

  • @jaysingh6066
    @jaysingh6066 8 месяцев назад

    How does using tie cell protect gate ?

  • @user-hf5kg8wi5z
    @user-hf5kg8wi5z 8 месяцев назад

    while there will be space in standard cells there discontinuity in power supply and n well so there will be drc violations to follow, in order to follow those drc rules we are using this filler cells to continue the power supply and n well

  • @khabylameyt5018
    @khabylameyt5018 8 месяцев назад

    Can you tell me what kind of simulator that we use in cadence Is spectre one if them??

  • @mekalagowthami162
    @mekalagowthami162 8 месяцев назад

    Sir.. can you tell... How we will get know about MCP. Is there any command to check what are the MCP in our design..(consider we didn't set MCP in sdc fie)